1. Field of the Invention
This invention relates to a bipolar transistor and a method of manufacturing the same, and more particularly to a bipolar CMOS device and a method of manufacturing the same.
2. Description of the Related Art
Recently, due to the demand for high integration and high speed operation of semiconductor devices, BiCMOS devices, which are combinations of bipolar transistors and CMOS devices, have attracted public attention. The conventional method of manufacturing BiCMOS devices and drawbacks thereof will be described below with reference to FIGS. 1A to 1E.
FIGS. 1A to 1E show steps of forming the basic elements of a BiCMOS devices, i.e., an NMOS, PMOS, and an NPN bipolar transistor, on a same silicon substrate. First, as shown in FIG. 1A, an antimony diffusion layer 2 with a high concentration is formed within a selective region in the silicon substrate 1. Thereafter, an epitaxial silicon layer 3 is grown on the silicon substrate 1, so that the antimony diffusion layer 2 is buried. The epitaxial silicon layer has to be low impurity concentration so as to form NMOS and PMOS transistors together with a bipolar transistor, as will be explained later.
Next, as shown in FIG. 1B, a P-well 5, an N-well 6 and a bipolar N-well 7 are formed in the epitaxial silicon layer 3 by means of ion implantation and thermal diffusion. Subsequently, field insulating films 4 are formed between the adjacent well regions by selective oxidation method. Thereafter, a deep N+-diffusion layer 8 is formed so as to reach the antimony diffusion layer 2 by ion implantation and thermal diffusion. The N+-diffusion layer 8 is to be connected to the collector electrode of the bipolar transistor in order to decrease the collector resistance. Then, channel ions are injected into the well regions so as to control the impurity concentrations of the channels, in order to adjust the threshold voltages of the NMOS transistor and the PMOS transistor.
Thereafter, as shown in FIG. 1C, after forming a gate oxide film, a polysilicon film is deposited by the LPCVD method, and unnecessary portions of the polysilicon film are removed by photolithography and reactive ion etching. As a result, an NMOS gate 9 and a PMOS gate 10 are formed. Subsequently, a P--base layer 13 is formed by ion implantation, then an NMOS N.sup.+ -diffusion source 9a, an NMOS N.sup.+ -diffusion drain layer 9b, a PMOS P.sup.+ -diffusion source layer 10a, a PMOS P.sup.+ -diffusion drain layer 10b, a P.sup.+ -base layer 11 and a N.sup.+ -collector layer 12 are formed by ion implantation. The regions in which ion implantation is not performed are covered with a resist film, then a first interlayer insulating film 14 is deposited on the entire surface by a CVD method.
Then, as shown in FIG. 1D, an opening is formed in that portion of the first interlayer insulating film 14 where the emitter of the bipolar transistor is to be formed and polysilicon is deposited in the opening to form an emitter. The polysilicon layer thus formed is patterned by photolithography and reactive ion etching, thus forming an emitter polysilicon layer 15. N-type impurity such as phosphorus are injected into the emitter polysilicon layer 15 by ion implantation, and diffused within the P.sup.- -base layer 13. Thus, an N.sup.+ -diffusion emitter layer 16 is formed.
Next, as shown in FIG. 1E, a second interlayer insulating film 17 is deposited on the entire surface. Openings are formed in the portions of the film 17 in which electrodes are to be formed. An NMOS source electrode 18a, an NMOS drain electrode 18b, a PMOS source electrode 19a, a PMOS drain electrode 19b, a emitter electrode 20a, a base electrode 20b, and a collector electrode 20c are formed via the openings. An insulative protecting film 21 is then deposited on the entire surface. Thus, NMOS, PMOS, and NPN bipolar transistors are obtained. The antimony diffusion layer 2 with a high concentration and the N+-diffusion layer 8 lower a collector resistance of the bipolar transistor and thus function as a low-resistant electrode wiring.
The most difficult drawback of the above conventional method is that, in order to lower the collector resistance of the bipolar transistor, the antimony diffusion layer 2 and the epitaxial silicon layer 3 must be formed. Since the steps of forming these layers are added to the steps of forming the CMOS devices, the manufacturing costs increase. In addition, the step of growing the epitaxial silicon layer 3 requires a difficult technique. More specifically, the epitaxial silicon layer 3 must be completely crystallized and accurately formed to a desired thickness, and the impurity concentration also must be controlled accurately. It is very difficult to maintain the crystallization of the epitaxial silicon layer 3, so that defects such as stacking faults frequently occur. These defects result in the low yield and low reliability of the device.